Tanner L-Edit Pro

Tanner L-Edit Pro

Tanner EDA’s L-Edit Pro meets your needs by combining the fastest rendering
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Tanner EDA’s L-Edit Pro meets your needs by combining the fastest rendering available with powerful features that exceed the needs of the most demanding user. This leading analog/mixed signal IC design tool enables you to get started with minimal training. You can draw and edit quickly, with fewer keystrokes and mouse clicks than other layout tools. Using powerful features such as interactive DRC, object snapping, and alignment, you can work more efficiently to save time and money.
L-Edit Pro includes L-Edit for layout editing, Interactive DRC for real-time design rule checking during editing, Standard DRC for hierarchical DRC, Standard Extract for netlist extraction, Standard LVS for layout versus schematic, Node Highlighting for highlighting all geometry associated with a node and SPR for standard cell place & route.
Features:
* L-Edit allows you to setup your technology information quickly by importing Cadence® Virtuoso® and Laker™ technology and display files.
* L-Edit is a complete environment for hierarchical physical layout with all-angle and curved polygons and performing AND, OR, XOR, Subtract, Grow, and Shrink on groups of objects.
* L-Edit’s parameterized cells, T-Cells, allow you to create versatile cells that consist of user-defined input parameters and layout-generating code which can be created automatically from layout.
* L-Edit Interactive DRC displays the spacing distance in real time while the layout is edited, helping you create compact, error-free layouts the first time.
* Quickly visualize node connectivity with L-Edit Node Highlighting so you can quickly find and fix LVS problems
* Standard DRC is an all-angle, hierarchical design rule checker that can be configured for through an easy to use graphical interface.
* Standard Extract generates a flat SPICE netlist from layout for LVS or post-layout simulation
* Standard LVS accurately and efficiently compares two SPICE netlists to determine whether they contain equivalent circuit descriptions including merging of devices and matching of device parameter values.
* SPR performs standard cell place and route, padframe generation, and pad routing.

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